Yes, the interrupt vector table is a list of function pointers (addresses). The table is located at a specific address defined by the processor. Each address in the table corresponds to the starting addresses of an interrupt service routine. When a processor interrupt occurs the processor fetches the address located at the specified interrupt location and initiates the interrupt entry sequence to jumps to that address.
The vector table may be created in C or assembler. It is important that it is linked to correspond with the interrupt vector addresses specified by the a particular chip.
A simple abbreviated HC12 example might look similar to the following:
Redefine a section for the vector table to simply the link process. You can also remove the #pragma lines and link using the .const section.
#pragma section const {vectors}
extern void swi_isr(void);
extern void illeagal_isr(void);
extern void cop_isr(void);
extern void cop_clock_isr(void);
extern void _stext(void);
void (* const vector[])() =
{
swi_isr,
illeagal_isr,
cop_isr,
cop_clock_isr,
_stext
};
#pragma section const {};
where swi_isr, illeagal_isr, cop_isr, cop_clock_isr and __stext are interrupt service routine functions defined with the @interrupt modifier. These ISR routines may typically defined in other source modules.
Using either version of the vector table you then link with the following segment line. The two lines below are often the last two lines in the link file.
+seg .vectors -b0xFFF6 #Sets the start of the vector table to 0xFFF6 - vector.o defines the last 5
vector.o # vectors of most HC12 family members
where vector.o is the compiled or assembled version of vector.c or vector.s.
Using an assembly language vector table instead of the C version, it might look similar to the following:
.vectors: section .data
xref swi_isr, illeagal_isr, cop_isr, cop_clock_isr, __stext
dc.w
dc.w
dc.w
dc.w
dc.w
_swi_isr
_illeagal_isr
_cop_isr
_cop_clock_isr
__stext
end
